 Functional verification培訓 |
| 入.學.要.求 |
|
學員學習本課程應具備下列基礎知識：
◆ 電路系統的基本概念。 |
|
班.級.規.模.及.環.境 |
|
為了保證培訓效果，增加互動環節，我們堅持小班授課，每期報名人數限5人，多余人員安排到下一期進行。 |
|
上課時間和地點 |
上課地點：【上海】：同濟大學(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：深圳大學成教院/ 電影大廈(地鐵一號線大劇院站)【北京分部】：福鑫大樓/北京中山學院 【武漢分部】：佳源大廈（高新二路） 【南京分部】：金港大廈(和燕路)
【成都分部】：領館區1號（中和大道）
最近開課時間(連續班/周末班/晚班）：Functional verification培訓：2025年12月15日..以質量贏得尊重節假日班火熱報名中.....實戰培訓......直播、現場培訓皆可....用心服務..............--即將開課----即將開課，請咨詢客服。 |
|
學時 |
◆課時： 共6天,36學時
◆外地學員：代理安排食宿（需提前預定）
☆合格學員免費頒發相關資格證書，提升您的職業資質
作為最早專注于嵌入式培訓的專業機構，曙海嵌入式學院提供的證書得到本行業的廣泛認
可，學員的能力得到大家的認同。
☆合格學員免費推薦工作
★實驗設備請點擊這兒查看★ |
|
.最.新.優.惠. |
|
◆團體報名優惠措施：兩人95折優惠，三人或三人以上9折優惠 。注意：在讀學生憑學生證，即使一個人也優惠500元。 |
|
.質.量.保.障. |
|
1、培訓過程中，如有部分內容理解不透或消化不好，可免費在以后培訓班中重聽；
2、培訓結束后,培訓老師留給學員手機和Email,免費提供半年的技術支持，充分保證培訓后出效果；
3、培訓合格學員可享受免費推薦就業機會。 ☆合格學員免費頒發相關工程師等資格證書，提升您的職業資質。專注高端培訓13年，曙海提供的證書得到本行業的廣泛認可，學員的能力得到大家的認同，受到用人單位的廣泛贊譽。 |
Functional verification培訓
|
第一階段 Incisive Comprehensive Coverage
Course Description
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.
The course discusses the collection and analysis of the following types of coverage:
- Code (block, expression, toggle, state, and arc) coverage
- Data-oriented functional coverage using SystemVerilog covergroups
- Control-oriented functional coverage using PSL and SystemVerilog assertions
Learning Objectives
After completing this course you will be able to:
- Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs
第二階段 Incisive SystemC, VHDL, and Verilog Simulation
Course Description
This course addresses Incisive? mixed-language (SystemC?, VHDL, and Verilog?) event-driven digital simulation. The course takes you through the compilation, elaboration, simulation, and interactive debug process, at each step explaining the most commonly used options. This course treats the SystemC, VHDL, and Verilog languages equivalently. You can do the labs in your choice of language.
Learning Objectives
After completing this course you will be able to:
- Compile, elaborate, link, and simulate a design: Understand how to specify the inputs and outputs at each phase, configure the design, and control each process for effectiveness and optimal performance.
- Debug a design with the textual interactive simulation interface: Briefly examine most of the interactive commands for the purpose of understanding what capabilities are available and how you can use them in a script to drive batched regression tests; practice these capabilities in the context of a scripted debug scenario.
- Debug a design with the graphical interactive simulation interface: Examine many of the capabilities of the feature-rich SimVision graphical simulation analysis environment; practice these capabilities in the context of a scripted debug scenario.
- Utilize some of the other tools available to assist your simulation-related efforts to: Verify your platform's patch level, protect your intellectual property, “lint” your design and filter and sort the analysis report, manage your library of compiled design objects, compare simulation traces, package your design for transmittal, and much more.
- Optionally: Understand the issues involved with mixed-language instantiation, simulation, and debugging; examine the mechanics of interconnecting components of multiple languages; choose and simulate a mixed-language design configuration containing at least one HDL component and at least one SystemC component.
|
|
|
課程表 聯系我 在線聊 報名 付款 我們 QQ聊 切換寬屏